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general description the MAX15569 step-down controller consists of one multiphase regulator. the multiphase cpu regulator uses maxims unique 2-phase quicktune-pwm constant on- time architecture. the 2-phase cpu regulator runs 180 out-of-phase for true interleaved operation, minimizing input capacitance. the devices vr is controlled by writing appropriate data into a function-mapped register file. output volt - ages are dynamically changed through a 2-wire, fast i 2 c interface (clock, data), allowing the switching regula - tor to be programmed to different voltages. a slew- rate controller allows controlled voltage transition and controlled soft-start. the regulator runs in a unique smart, low-power pulse-skipping-state algorithm for best efficiency over the full load range and the best transient response with respect to common pulse- skipping methods. the device includes multiple fault-protection features: output overvoltage protection (ovp), undervoltage pro - tection (uvp), and thermal protection. when any of these fault-protection features detect a fault condition, the con - troller shuts down. a multifunction int output monitors output voltage, overcurrent (oc), overrange (voutmax), and thermal faults ( vrhot ). the controller has a programmable switching frequency, allowing 300khz to 1400khz per each phase of opera - tion. the controller operates with a wide variety of drivers and mosfets, such as the max15492 mosfet driver with standard mosfets, or with the power stage that integrates the drivers and mosfets together in a single device. applications arm core power supply ultrabook? and tablet core supplies voltage-positioned step-down converter multiphase dc-dc controllers beneits and features multiphase controller maximizes processor performance ? 2-phase quicktune-pwm cpu core regulator ? output-voltage control ? active load-line amplifier with adjustable gain ? 5mv fb accuracy over line and load ? programmable slew rate and soft-start ? accurate current balance and current limit ? true differential remote output sense ? 8-bit adc digitizes current sense to store in current monitor register transient phase overlap reduces output capacitance programmable functionality allows optimized design performance ? programmable 300khz to 1400khz switching frequency ? programmable soft-shutdown (2k discharge switch) ? i 2 c serial-interface control robust protection for reliable operation ? overcurrent, output-voltage overrange, overvoltage, undervoltage, and thermal-fault protection ? system status register ? multifunction int output ? 4.5v to 24v battery input range ordering information appears at end of data sheet. MAX15569 2-phase/1-phase quicktune-pwm controller with serial i 2 c interface 19-6646; rev 1; 2/15 ultrabook is a trademark of intel corporation. evaluation kit available downloaded from: http:///
v tt to agnd ........................................ -0.3v to (v bias + 0.3v) bias to agnd ......................................................... -0.3v to +6v en, scl, sda to agnd .......................................... -0.3v to +6v csp1, csn1, csp2, csn2 to agnd ..................... -0.3v to +6v fb, fbac, imon to agnd .................... -0.3v to (v bias + 0.3v) drvpwm1, drvpwm2 to pgnd ......... -0.3v to (v bias + 0.3v) drvskp to pgnd ................................. -0.3v to (v bias + 0.3v) int , therm to agnd ............................................ -0.3v to +6v ic to agnd .............................................................. -0.3v to +6v gnds to agnd .................................................... -0.3v to +0.3v pgnd to agnd .................................................... -0.3v to +0.3v ton to agnd ........................................................ -0.3v to +26v continuous power dissipation (t a = +70c) tqfn (derate 27.8mw above +70c) ............................. 2.2w operating temperature range ......................... -40c to +105c junction temperature ...................................................... +150c storage temperature range ............................ -65c to +165c lead temperature (soldering, 10s) ................................. +300c soldering temperature (reflow) ....................................... +260c tqfn junction-to-ambient thermal resistance ( ja ) .......... 36c/w junction-to-case thermal resistance ( jc ).. ........ 3c/w (note 1) (circuit of figure 1 . v in = 10v, v bias = 5v, v tt = 1.8v, en = bias, gnds = agnd, v fbac = v fb = v csp_ = v csn_ = 1v [setvout register 0x07h set to 0x33h]. t a = 0c to +85c, unless otherwise noted. typical values are at +25c. all devices 100% tested at +25c. limits over temperature are guaranteed by design.) parameter symbol conditions min typ max units bias currents bias voltage range v bias 4.75 5.25 v i 2 c interface supply (v tt ) v tt 1.6 4.0 v quiescent supply current (bias) i bias skip mode, measured at bias, v tt = 1.8v; fb forced above the regulation point, en = bias 2 5 ma shutdown supply current (bias) measured at bias, en = gnd,v tt = 1.8v or gnd, t a = +25c 6 a v tt bias current i vtt v bias = high, en = low, t a = +25c 3 a v bias = high, en = high, t a = +25c 50 pwm controller dc output voltage accuracy (note 2) t a = +25c; measured at fb, with respect to gnds; includes load regulation error dac codes from 0.50v to 1.60v -5 +5 mv dc output voltage accuracy (note 2) measured at fb, with respect to gnds; includes load regulation error dac codes from 0.50v to 1.40v -8 +8 mv dac codes from 1.40v to 1.60v -0.7 +0.7 % line regulation error v bias = 4.75v to 5.25v, v in = 5.5v to 20v 0.1 mv MAX15569 2-phase/1-phase quicktune-pwm controller with serial i 2 c interface www.maximintegrated.com maxim integrated 2 note 1: package thermal resistances were obtained using the method described in jedec specification jesd51- 7, using a four-layer board. for detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial . absolute maximum ratings stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. package thermal characteristicselectrical characteristics (0c to +85c) downloaded from: http:///
(circuit of figure 1 . v in = 10v, v bias = 5v, v tt = 1.8v, en = bias, gnds = agnd, v fbac = v fb = v csp_ = v csn_ = 1v [setvout register 0x07h set to 0x33h]. t a = 0c to +85c, unless otherwise noted. typical values are at +25c. all devices 100% tested at +25c. limits over temperature are guaranteed by design.) parameter symbol conditions min typ max units gnds input range -200 +200 mv gnds gain a gnds 0.97 1.00 1.03 v/v gnds input bias current i gnds t a = +25c -0.5 +0.5 a ton shutdown current en = agnd, v in = 24v, v bias = 0v or 5v, t a = +25c 0.01 0.1 a drvpwm_ on-time (note 3) t on measured at drvpwm_, r ton = 136.3k (1400khz) 60 71 82 ns measured at drvpwm_, r ton = 200k (1000khz) 92 104 114 measured at drvpwm_, r ton = 326.7k (600khz) 141 166 192 minimum off-time (note 3) t off(min) measured at drvpwm_ 100 133 ns slew-rate accuracy (see table 8 for soft-start and regular slew-rate combinations) slew rate = 3.5mv/s , 4.5mv/s, 5.5mv/s, 7mv/s, 9mv/s, 11mv/s, 14mv/s, 18mv/s, 22mv/s, 28mv/s, 36mv/s, 44mv/s (nominal) -20 % fault protection upper int and output overvoltage-protection trip threshold v ovp soft-start completed, measured at fb 1.78 1.83 1.88 v upper int and output overvoltage propagation delay t ovp fb forced 25mv above trip threshold 5 s lower int and output undervoltage-protection trip threshold v uvp measured at fb, with respect to unloaded output voltage -300 -250 -200 mv lower int propagation delay fb forced 25mv below trip threshold 5 s output undervoltage propagation delay t uvp fb forced 25mv below trip threshold 100 200 350 s int output low voltage i sink = 4ma 0.3 v int leakage current high state, int forced to 5v, t a = +25c 1 a int startup delay and transitions blanking time t int measured from the time when fb reaches the target voltage 4 s v bias undervoltage-lockout threshold v uvlo rising edge, 50mv typical hysteresis, controller disabled below this level 4.3 4.5 4.7 v MAX15569 2-phase/1-phase quicktune-pwm controller with serial i 2 c interface www.maximintegrated.com maxim integrated 3 electrical characteristics (0c to +85c) (continued) downloaded from: http:///
(circuit of figure 1 . v in = 10v, v bias = 5v, v tt = 1.8v, en = bias, gnds = agnd, v fbac = v fb = v csp_ = v csn_ = 1v [setvout register 0x07h set to 0x33h]. t a = 0c to +85c, unless otherwise noted. typical values are at +25c. all devices 100% tested at +25c. limits over temperature are guaranteed by design.) parameter symbol conditions min typ max units thermal protection therm resistor r therm internal pullup resistance 5.24 5.35 5.48 k vrhot trip threshold measured at therm, with respect to v bias falling edge; specify as % error for all temp max dac code settings; typical hysteresis = 100mv, t a = +25c to +100c 49.5 50.5 % therm sampling period 5% duty cycle 0.75 1.1 ms internal thermal-fault shutdown threshold t tshdn typical hysteresis = +15 c 160 c valley current limit and droop valley current-limit threshold voltage (positive) v ilim v csp_ - v csn_ 35 38 41 mv oc_alarm valley current threshold voltage (positive, csp1 only) v oc_alarm v csp1 - vcsn1 20 23 26 mv current-balance offset voltage -1.8 +1.8 mv current-sense common-mode input range csp1, csn1, csp2, csn2 0.5 1.6 v current-sense input current csp1, csn1, csp2, csn2, t a = +25c -0.12 +0.12 a discharge switch resistance csn1 only 2 k fb input current t a = +25c -0.2 +0.2 a phase 2 disable threshold csp2 3 v bias - 1.0 v bias - 0.4 v droop ampliier (gmd) offset average (v csp_ - v csn_ ) at i fbac = 0ma -1.0 +1.0 mv droop ampliier (gmd) transconductance g m(fbac) d i fbac / d (v csp_ - v csn_ ), measured at fbac 1.182 1.2 1.218 a/mv current monitor (imon) current monitor output current for typical full-load conditions i imon (v csp_ - v csn_ ) = 25mv 124.2 128 131.8 a current monitor gain g m(imon) d i imon / d (v csp_ - v csn_ ), measured at imon 4.8 5.12 5.44 a/mv current monitor clamp voltage imon 3.2 3.6 v driver control drvpwm_, drvskp# output logic-high voltage v oh_drv i source = 3ma v bias - 0.4 v drvpwm_, drvskp# output logic-low voltage v ol_drv i sink = 3ma 0.4 v drvpwm_ output midlevel voltage 1.6 2.3 v MAX15569 2-phase/1-phase quicktune-pwm controller with serial i 2 c interface www.maximintegrated.com maxim integrated 4 electrical characteristics (0c to +85c) (continued) downloaded from: http:///
(circuit of figure 1 . v in = 10v, v bias = 5v, v tt = 1.8v, en = bias, gnds = agnd, v fbac = v fb = v csp_ = v csn_ = 1v [setvout register 0x07h set to 0x33h]. t a = 0c to +85c, unless otherwise noted. typical values are at +25c. all devices 100% tested at +25c. limits over temperature are guaranteed by design.) parameter symbol conditions min typ max units enable logic (en) en input high voltage v ih_en 0.7 x v tt v en input low voltage v il_en 0.33 v en input current i en t a = +25c -1 +1 a power-up calibration delay t cal 850 s enable to startup delay t strt en to irst switching edge (fully discharged output) 150 s i 2 c interface (sda, scl) i 2 c input low voltage v il 0.4 v i 2 c input high voltage v ih 0.7 x v tt v i 2 c output low level (sda only) v ol open-drain output, 3ma pullup to v tt 0.4 v i 2 c logic inputs leakage current t a = +25c -1 +1 a i 2 c timing requirements i 2 c clock frequency 3.4 mhz hold time repeated start condition t hd_sta (note 4) 160 ns scl low period t low (note 4) 160 ns scl high period t high (note 4) 60 ns setup time repeated start condition t su_sta (note 4) 160 ns sda hold time t hd_dat (note 4) 0 70 ns sda setup time t su_dat (note 4) 10 ns setup time for stop condition t su_sto (note 4) 160 ns MAX15569 2-phase/1-phase quicktune-pwm controller with serial i 2 c interface www.maximintegrated.com maxim integrated 5 electrical characteristics (0c to +85c) (continued) downloaded from: http:///
(circuit of figure 1 . v in = 10v, v bias = 5v, v tt = 1.8v, en = bias, gnds = agnd, v fbac = v fb = v csp_ = v csn_ = 1v [setvout register 0x07h set to 0x33h]. t a = -40c to +105c, unless otherwise noted.) parameter symbol conditions min typ max units bias currents bias voltage range v bias 4.75 5.25 v i 2 c interface supply (v tt ) v tt 1.6 4.0 v quiescent supply current (bias) i bias skip mode, measured at bias, v tt = 1.8v; fb forced above the regulation point; en = bias 5 ma pwm controller dc output voltage accuracy (note 2) measured at fb, with respect to gnds; includes load regulation error dac codes from 0.50v to 1v -10 +10 mv dac codes from 1v to 1.60v -1.0 +1.0 % gnds gain a gnds 0.97 1.03 v/v drvpwm_ on-time (note 3) t on measured at drvpwm_, r ton = 136.3k, (1400khz) 60 82 ns measured at drvpwm_, r ton = 200k, (1000khz) 92 114 measured at drvpwm_, r ton = 326.7k, (600khz) 141 192 minimum off-time (note 3) t off(min) measured at drvpwm_ 133 ns slew-rate accuracy (see table 8 for soft-start and regular slew-rate combinations) slew rate = 3.5mv/s , 4.5mv/s, 5.5mv/s, 7mv/s, 9mv/s, 11mv/s, 14mv/s, 18mv/s, 22mv/s, 28mv/s, 36mv/s, 44mv/s (nominal) -20 % fault protection upper int and output overvoltage-protection trip threshold v ovp soft-start completed; measured at fb 1.78 1.88 v lower int and output undervoltage-protection trip threshold v uvp measured at fb, with respect to unloaded output voltage -300 -200 mv output undervoltage propagation delay t uvp fb forced 25mv below trip threshold 100 350 s int output low voltage i sink = 4ma 0.3 v v bias undervoltage-lockout threshold v uvlo rising edge, 50mv typical hysteresis; controller disabled below this level 4.3 4.7 v MAX15569 2-phase/1-phase quicktune-pwm controller with serial i 2 c interface www.maximintegrated.com maxim integrated 6 electrical characteristics (-40c to +105c) downloaded from: http:///
(circuit of figure 1 . v in = 10v, v bias = 5v, v tt = 1.8v, en = bias, gnds = agnd, v fbac = v fb = v csp_ = v csn_ = 1v [setvout register 0x07h set to 0x33h]. t a = -40c to +105c, unless otherwise noted.) parameter symbol conditions min typ max units thermal protection therm resistor r therm internal pullup resistance 5.24 5.48 k vrhot trip threshold measured at therm, with respect to v bias falling edge; specify as % error for all temp max dac code settings; typical hysteresis = 100mv; t a = +25c to +105c 49.5 50.5 % valley current limit and droop valley current-limit threshold voltage (positive) v ilim v csp_ - v csn_ 35 41 mv oc_alarm valley current threshold voltage (positive, csp1 only) v oc_alarm v csp1 - v csn1 20 26 mv current-balance offset voltage -2.5 +2.5 mv current-sense common-mode input range csp1, csn1, csp2, csn2 0.5 1.6 v phase 2 disable threshold csp2 3 v bias - 0.4 v droop ampliier (gmd) offset average (v csp_ - v csn_ ) at i fbac = 0ma -1.0 +1.0 mv droop ampliier (gmd) transconductance g m(fbac) d i fbac / d (v csp_ - v csn_ ), measured at fbac 1.176 1.224 a/mv current monitor (imon) current monitor output current for typical full-load conditions i imon (v csp_ - v csn_ ) = 25mv 122.2 133.8 a current monitor gain g m(imon) d i imon / d (v csp_ - v csn_ ), measured at imon 4.8 5.44 a/mv driver control drvpwm_, drvskp output logic-high voltage v oh_drv i source = 3ma v bias - 0.4 v drvpwm_, drvskp output logic-low voltage v ol_drv i sink = 3ma 0.4 v drvpwm_ output midlevel voltage 1.6 2.3 v enable logic (en) en input high voltage v ih_en 0.7 x v tt v en input low voltage v il_en 0.33 v MAX15569 2-phase/1-phase quicktune-pwm controller with serial i 2 c interface www.maximintegrated.com maxim integrated 7 electrical characteristics (-40c to +105c) (continued) downloaded from: http:///
(circuit of figure 1 . v in = 10v, v bias = 5v, v tt = 1.8v, en = bias, gnds = agnd, v fbac = v fb = v csp_ = v csn_ = 1v [setvout register 0x07h set to 0x33h]. t a = -40c to +105c, unless otherwise noted.) note 2: the equation for the target voltage v target is: v target = the output of slew control dac, where v dac = 0v for shutdown, v dac = v boot during startup; otherwise v dac = setvout. the output voltages for all possible codes are given in table 3 . note 3: on-time and minimum off-time specifications are measured from 50% rise to 50% fall at the drvpwm_ p in. actual in-circuit times can be different due to mosfet driver characteristics. note 4: guaranteed by design. not production tested. parameter symbol conditions min typ max units i 2 c timing requirements i 2 c clock frequency 3.4 mhz hold time repeated start condition t hd_sta (note 4) 160 ns scl low period t low (note 4) 160 ns scl high period t high (note 4) 60 ns setup time repeated start condition t su_sta (note 4) 160 ns sda hold time t hd_dat (note 4) 0 70 ns sda setup time t su_dat (note 4) 10 ns setup time for stop condition t su_sto (note 4) 160 ns 2324 22 21 87 9 fbac imon therm v tt 10 gnds drvpwm2 drvpwm1 pgnd ton bias 1 2 n.c. 4 5 6 17 18 16 14 13 csn2 csp2 *ep i.c. (bias) scl sda agnd MAX15569 fb drvskp 3 15 csn1 20 11 i.c. (bias) csp1 19 12 en int tqfn (4mm x 4mm) top view + *ep = exposed pad. connect to ground. MAX15569 2-phase/1-phase quicktune-pwm controller with serial i 2 c interface www.maximintegrated.com maxim integrated 8 electrical characteristics (-40c to +105c) (continued)pin coniguration downloaded from: http:///
pin name function 1 gnds ground remote-sense input. connect gnds to the ground-sense pin of the cpu located directly at the point of load. gnds internally connects to an internal transconductance ampliier that adjusts the feedback voltage to compensate for voltage drops between the local controller ground and the remote load ground. 2 fbac output of the ac voltage positioning transconductance ampliier. the effective impedance (z fbac ) between this pin and the positive side of the remote-sensed output voltage sets the transient ac droop. see the load-line ampliier (steady state and ac droop) section. fbac is high impedance in shutdown. 3 fb feedback-sense input. an integrator on fb corrects for output ripple and ground-sense offset. connect a resistor (r fb ) between fb and the positive output of the remote sense (output) to set the dc steady-state droop. the impedance from fbac to fb sets the current-loop gain over frequency, which dominates stability. see the load-line ampliier (steady state and ac droop) section. 4 imon current monitor output. the output current at imon is: i imon = g m(imon) x (csp_ - csn_) where g m(imon) = 5.12ms (typ). an external resistor (r imon ) between imon and gnds sets the current monitor output voltage: v imon = i load x rsense x g m(imon) x r imon where r sense is the value of the effective current-sense resistance. choose r imon so that v imon is 2.56v at the desired full current. imon is high impedance when in shutdown. 5 therm thermal-sense input. connect a 100k? ntc with = 4250k from therm to agnd. the ntc at therm is used to determine the temperature of the power stages. place near the hottest region of the regulator (typically the mosfets and inductor of phase 1). the vrhot status bit (d5) activates when the ntc resistance drops to 5.68k? (100c when using a 100k? ntc with = 4250k). 6 v tt interface logic supply. power v tt from a 1.8v to 3.3v 10% source with a compliance of at least 1ma. decouple v tt with at least 1f of ceramic capacitance. 7 agnd analog ground 8 sda i 2 c serial-data input/output. open-drain i/o pin. connect an external pullup resistor between sda and the supply used to power the i 2 c interface (v tt ). 9 scl i 2 c serial-data clock input 10, 11 i.c. internally connected. connect to bias. 12 en controller enable input. drive en high or connect en to bias for normal operation. pull to ground to put the controller into its 7a (max) standby state (i 2 c interface active, regulator not switching).during soft-start, the controller slowly ramps the output voltage up to the boot voltage with the selected slew rate (register 0x06, default is 4.5mv/s for start-up and 9mv/s for normal operation). during the transition from normal operation to standby, the output is discharged through a 2k internal discharge mosfet on csn1. toggling en does not reset the fault latches. cycle power (v tt or bias) to trigger the power-on reset (por) to clear the fault conditions. the en input is rated for up to 5.5v. MAX15569 2-phase/1-phase quicktune-pwm controller with serial i 2 c interface www.maximintegrated.com maxim integrated 9 pin description downloaded from: http:///
pin name function 13 bias analog and driver supply voltage input. bias provides the supply voltage for the drivers pwm and skip control outputs. connect bias to the same supply used by the external drivers (typically the 4.5v to 5.5v system supply voltage). bypass bias to power ground with a local 1f or greater ceramic capacitor. 14 pgnd power ground 15 drvpwm1 direct-drive pwm output for controlling the external first-phase driver. the drvpwm1 push-pull output drives the signal between bias and pgnd. drvpwm1 is high impedance in shutdown and after fault conditions (output overvoltage/undervoltage or thermal fault). 16 drvskp external driver skip-mode control output. the drvskp output is low in standby. drvskp goes high when the controller detects an output overvoltage fault condition, or during dynamic output-voltage transitions. for applications operating with forced-pwm operation, disable the driver zero-crossing detection and leave drvskp unconnected. 17 drvpwm2 direct-drive pwm output for controlling the external second-phase driver. the drvpwm2 push-pull output drives the signal between bias and pgnd. drvpwm2 is high impedance in shutdown and after fault conditions (output overvoltage, output undervoltage, or thermal fault). 18 ton switching frequency adjustment input. an external resistor between the input power source and ton sets the switching period (per phase) according to the following equation: f sw = (r ton + 6.5k?) x 5pf where f sw = 1/f sw is the nominal switching frequency. a 200k? resistor provides a typical operating frequency of 1mhz. ton is high impedance in shutdown. 19 int open-drain interrupt output. int is triggered by latched faults (output undervoltage, output overvoltage, thermal shutdown), sticky alarms (internal overcurrent (oc), non-sticky alarms (voltage regulator hot (vrhot), and vid code violations (voutmax)). the fault conditions and alarms can be masked through register 0x05h. masking these signals only prevents int from being asserted; the status register still asserts when any of these conditions occur. int remains high in standby mode (en pulled low) to reduce power through the pullup resistor. int is pulled low during soft-start. after completing the soft-start sequence, int becomes high impedance as long as fb remains in regulation and there are no active alarms. to obtain a logic signal, pull up int with an external resistor connected to a logic supply. 20 csp1 positive current-sense input for the first phase. 1) connect csp1 to the positive side of the current-sense resistor or the dcr sense ilter capacitor of phase 1, as shown in figure 4. 2) connect csp1 to the iout pin of the smart power stage (max15515). a resistor across csp1 and csn1 sets the current-sense gain, as shown in figure 3. see the current sense section. 21 csn1 negative current-sense input for the first phase. connect csn1 to the negative side of the current-sense element, as shown in figure 4. an internal 2k discharge mosfet between csn1 and ground is enabled under an input uvlo or shutdown condition. 22 n.c. no connection internally MAX15569 2-phase/1-phase quicktune-pwm controller with serial i 2 c interface www.maximintegrated.com maxim integrated 10 pin description (continued) downloaded from: http:///
pin description (continued) pin name function 23 csn2 negative current-sense input for the second phase. connect csn2 to the negative side of the current-sense element, as shown in figure 4. 24 csp2 positive current-sense input for the second phase. 1) connect csp2 to the positive side of the current-sense resistor or the dcr sense ilter capacitor of phase 2, as shown in figure 4. 2) connect csp2 to the iout pin of the smart power stage (max15515). a resistor across csp2 and csn2 sets the current-sense gain, as shown in figure 3. see the current sense section. to disable phase 2, short csp2 to bias. ep exposed pad. the substrate of the controller is internally connected to the exposed pad. connect ep to the ground plane through multiple vias to maintain low thermal impedance. MAX15569 2-phase/1-phase quicktune-pwm controller with serial i 2 c interface www.maximintegrated.com maxim integrated 11 downloaded from: http:///
figure 1. MAX15569 typical application circuit (with max15492 driver and mosfet) max15492 bst dh lx dl 34 6 v dd 28 1 pwr pwr pwr pwr 5 18 13 1516 20 pwmskip gnd r imon 1% 0402 imon c imon 0402 ntc therm ton bias 10 i.c. 22 n.c. 12 vr_enable en 19 i 2 c interface int 8 sda 11 i.c. drvpwm1 drvskp 5v 5v to 20voutput output imonagnd pgnd ep ep r ton 1% 0402 2 fbac 3 fb 1 gnds agnd r fbac 1% 0402 r fb 1% 0402 r bst1 0 ? l1 c bst1 0 .1f c in 7 csp1 21 csn1 drvpwm2 csp2 csn2 54 7 14 scltherm 6 v tt c vcc 2.2f 6v r int 10k ? 5% 0402 r i2c 1k ? 5% 0402 5v bias 1.8v c out max15492 bst dh lx dl 34 6 v dd 28 1 pwr 5 1724 pwmskip gnd 5v v in r bst1 0 ? r10 10 ? 5% 0402 feedback filters remote output sense remote ground sense r11 10 ? 5% 0402 l2 c bst1 0 .1f c fbac 0 402 c fb 1nf 6v 0 402 agnd 7 23 pwr pwr power groundanalog ground MAX15569 c vcc 2.2f 6v c gnds 1nf 6v 0 402 ep MAX15569 2-phase/1-phase quicktune-pwm controller with serial i 2 c interface www.maximintegrated.com maxim integrated 12 downloaded from: http:///
type ref 2-phase design example (1mhz operation) operating conditions input voltage v in 5v to 20v output voltage v out 1v output current i out 20a (max), 14a rms load transient d i out 25a current limit i ocp 40a switching frequency f sw 1mhz number of phases n ph 2 components ton r ton 200k? 1% inductor l 0.2h/9.5m?/9.5a inductor (4.06mm x 4.55mm x 1.2mm) vishay ihlp-1616ab-1a mosfet driver drv max15492 high-side mosfet n h low-side mosfet n l current sense r cs bulk output capacitors (mid frequency) c out ceramic output capacitors (high frequency) c out 20 x 22f ceramic capacitors input capacitors c in 2 x 10f, 16v x5r ceramic capacitors fb droop setting r fbac = r fb = 1k? 1% c fbac = 4.7nf ac droop = -1.5mv/a dc droop = 0mv/a imon r imon , c imon r imon = 5.62k? 1% c imon = 47nf (260s time constant) therm ntc r therm 100k?, 5% ntc thermistor = 4250k (0603) murata ncp18wf104j03rb tdk ntcg163jf104j (0402) or panasonic ert-j1vr104j MAX15569 2-phase/1-phase quicktune-pwm controller with serial i 2 c interface www.maximintegrated.com maxim integrated 13 table 1. components for typical application circuit downloaded from: http:///
figure 2. functional block diagram phase 2 control trig trig q ton drvpwm1 intscl drvskptherm fb q minimum off-time one-shot one-shot on-time (phase 1) r q s bias set target en fb gndsagnd imon ccv digital core target 2 phase select trig 1 phase control skip MAX15569 set dac target fbac csp2 csn2 csp1 csn2 sdapgnd slope q csp1 drvpwm2 bias csn1csn2 csp2 on-time one-shot (phase 2) g m(cci) g m(cci) trig bias bias csp2 csn2 ilim csp1 csn1 ilim dac therm amp MAX15569 2-phase/1-phase quicktune-pwm controller with serial i 2 c interface www.maximintegrated.com maxim integrated 14 downloaded from: http:///
detailed description for system power management, the MAX15569 controller includes a current gauge and thermal status (vrhot) that can be monitored over the i 2 c interface. in addition, the devices multiple fault-protection features include: output overvoltage protection (ovp), undervoltage protection (uvp), and thermal protection. when any of these fault-protection features detect a fault condition, the controller shuts down. free-running constant on-time controller with input feed-forward the quicktune-pwm control architecture consists of a pseudo-fixed frequency, constant on-time, and current- mode regulator with voltage feed-forward ( figure 2 ). the control algorithm is simple; the high-side switch on-time is determined solely by a one-shot, whose period is inversely proportional to input voltage and directly proportional to the feedback voltage or the difference between the main and secondary inductor currents (see the on-time one- shot section). another one-shot sets a minimum off-time. the on-time one-shot triggers when the inverting input to the error comparator falls below the target voltage, the inductor current of the selected phase is below the valley current-limit threshold, and the minimum off-time one-shot times out. the regulator maintains 180 out-of- phase operation by alternately triggering the two phases after the error comparator drops below the output-voltage set point. switching frequency connect a resistor (r ton ) between ton and the input supply (v in ) to set the switching period (t sw = 1/f sw ) per phase using the following equation: t sw (r ton + 6.5k?) x 5pf high-frequency (600khz to 1.4mhz) operation optimizes the application for the smallest component size. a 200k? resistor sets a typical operating frequency of 1mhz. on-time one-shot the device contains fast, low-jitter, adjustable one-shots that set the respective high-side mosfet on-times through the drvpwm_ outputs. the one-shot for the main phase varies the on-time in response to the input and feedback voltage (v fb ). v fb equals the setvout voltage in steady-state. the main high-side switch on-time is inversely proportional to the input voltage as measured at v in , and proportional to v fb : sw fb on in (ignoring propag t a (v + 0.075v) t tion d v elays) = for setvout voltages below 0.9v, the device uses a fixed 0.9v instead to determine the on-time. switching frequency is reduced, improving low-voltage efficiency. sw on in t (0.9v + 0.075v) t= v the one-shot for the second phase varies the on-time in response to the input voltage and the difference between the main and the second inductor currents. two identi - cal transconductance amplifiers integrate the difference between the first and second current-sense signals. the respective error signals are used to correct the on-time of the high-side mosfets for the second phase and to maintain current balanced between the two phases. on-times translate only roughly to switching frequencies. the on-times guaranteed in the electrical characteristics section are influenced by parasitics in the conduction paths and propagation delays. the following equation shows the effect of the propagation delays on t on : sw fb on d(off) d(on) in t (v + 0.075v) t = +t -t v where t d(off) is the delay from the falling edge of the pwm signal to the to the time that the high-side mosfet turns off. t d(on) is the delay from the rising edge of the pwm signal to the time that the high-side mosfet turns on. for loads above the critical conduction point, where the dead-time effect (lx flying high and conducting through the high-side fet body diode) is no longer a factor, the actual switching frequency (per phase) is: out dis sw on in dis chg (v v ) f t (v v v ) + = ++ where v dis is the sum of the parasitic voltage drops in the inductor discharge and charge paths, including mosfet, inductor, and pcb resistances; v chg is the sum of the parasitic voltage drops in the inductor charge path, includ - ing high-side switch, inductor, and pcb resistances; and t on is the on-time as determined in the prior equation. 180 out-of-phase operation the two phases in the device operate 180 out-of-phase to minimize input and output filtering requirements, reduce emi, and improve efficiency. this effectively low - ers component countreducing cost, board space, and component power requirementsmaking this device ideal for high-power applications. the device shares the current between two phases that operate 180 out-of- phase under steady-state conditions. MAX15569 2-phase/1-phase quicktune-pwm controller with serial i 2 c interface www.maximintegrated.com maxim integrated 15 downloaded from: http:///
the instantaneous input current of each phase is effectively reduced, resulting in reduced input-voltage ripple, esr power loss, and rms ripple current (see the input capacitor selection section). therefore, the same performance can be achieved with fewer or less- expensive input capacitors.5v bias supply the quicktune-pwm controller requires an external 5v bias supply in addition to the system supply. typically, the system has a regulated 5v bias for interface (usb) or hard-drive support that can be used. the maximum current drawn from the 5v bias supply is provided in the electrical characteristics section. if the 5v bias supply is powered up prior to the system supply, the enable signal (en going from low to high) should be delayed until the system voltage is present to ensure startup. current sensethe device senses the inductor current of each phase, allowing the use of current-sense resistors, inductor dcr, or the current-sense signal provided by the external power stage (max15515). low-offset amplifiers are used for current balance, load-line gain, current monitor, and current limit. power stage current-sense support (max15515 only) the max15515 features a transconductance current- sense amplifier with a current monitor output (i out ) with an output current of: i out = a i lx where a is 10 -5 (typ) and i lx is the inductor current. i out is internally temperature compensated and therefore, external temperature compensation is not required. refer to the max15515 data sheet for more information. a resistor between csp_ and csn_ (see figure 3 ) sets the gain of the current-sense signal to the controller. figure 3. the MAX15569 using the max15515 internal current-sense method csp1csp2 csn2 fb imon bst lx csn1 MAX15569 max15515 fbac c bst a) MAX15569 and smart power stage (max15515) C with dc load regulation c out l imon bst lx max15515 c bst l r ilim2 r ilim1 r droop csp1csp2 csn2 fb imon bst lx csn1 MAX15569 max15515 fbac c bst b) MAX15569 and smart power stage (max15515) C no dc load regulation c out c fb l imon bst lx max15515 c bst l r ilim2 r ilim1 r fb r fbac MAX15569 2-phase/1-phase quicktune-pwm controller with serial i 2 c interface www.maximintegrated.com maxim integrated 16 downloaded from: http:///
inductor dcr and sense resistor current sense using the dc resistance (r dcr ) of the output inductor allows higher efficiency compared to using a current- sense resistor. the initial tolerance and temperature coefficient of the inductors dcr must be accounted for in the output-voltage droop-error budget and current monitor. this current-sense method uses an rc filter network to extract the current information from the output inductor (see figure 4 ). the rc network should match the time constant of the inductor (l/r dcr ): cs dcr r2 rr r1 r2 ?? = ?? + ?? and: dcr eq l1 1 r c r1 r2 ?? = + ?? ?? where r cs is the required current-sense resistance and r dcr is the inductors series dc resistance. use the typical inductance and r dcr values provided by the inductor manufacturer. to minimize the current-sense error, due to the leakage current of the current-sense inputs (i csp_ and i csn_ ), choose r1||r2 to be less than 2k? and use the previous equation to determine the sense capacitance (c eq ). choose capacitors with 5% tolerance and resistors with 1% tolerance specifications. temperature compensation is recommended for this cur - rent-sense method. see the load-line amplifier (steady state and ac droop) section for detailed information. when using a current-sense resistor for accurate output load-line control, the circuit requires a differential rc filter to eliminate the ac voltage step caused by the equivalent series inductance (l esl ) of the current-sense resistor (see figure 4 ). the esl-induced voltage step might affect the average current-sense voltage. the time constant of the rc filter should match the l esl /r sense time constant formed by the parasitic inductance of the current-sense resistor: esl eq eq sense l cr r = where l esl is the equivalent series inductance of the current-sense resistor, r sense is the current-sense resistance value, and c eq and r eq are the time-constant matching components. figure 4. sense resistor and dcr current-sense methods lx bst csp_ power stage MAX15569 inductor csn_ r1 l r2 c eq r dcr c bst a) lossless inductor sensing for thermal compensation:r2 should consist of an ntc resistor in series with a standard thin-film resistor r cs = r dcr r 2 r 1 + r 2 r dcr = l c eq 1 r 1 1 r 2 + c out lx bst csp_ power stage MAX15569 sense resistor csn_ l esl l c eq r sense c bst b) output series resistor sensing c eq r eq = l esl r sense r1 MAX15569 2-phase/1-phase quicktune-pwm controller with serial i 2 c interface www.maximintegrated.com maxim integrated 17 downloaded from: http:///
current balance the device integrates the difference between the current- sense voltages and adjusts the on-time of the second phase to maintain current balance. the current balance relies on the accuracy of the current-sense signals across the current-sense resistor, inductor dcr, or provided by the power stage (max15515). with active current balancing, the current mismatch is determined by the current-sense element values and the offset voltage of the transconductance amplifiers: os(ibal) os(ibal) lmain lsec sense v i i -i r = = where r sense is the equivalent sense resistance across csp_, csn_, and v os(ibal) is the current-balance off - set specification in the electrical characteristics section. the worst-case current mismatch occurs immediately after a load transient due to inductor value mismatches, resulting in different di/dt for the two phases. the time it takes for the current-balance loop to correct the transient imbalance depends on the mismatch between the inductor values and switching frequency. current limit the current-limit circuit employs a valley current-sensing algorithm that senses the voltage across the current- sense inputs (csp_ and csn_). if the current-sense signal (v csp2 , v csn2 or v csp1 , v csn1 ) of the selected phase is above the current-limit threshold (v ilim ), the pwm controller does not initiate a new cycle for that phase until its inductor current drops below the valley current-limit threshold. since only the valley current is actively limited, the actual peak current is greater than the current-limit threshold by an amount equal to 1/2 the inductor ripple current: ( ) load lx peak i i =i + 2 d ( ) load lx valley i i =i - 2 d where : on in out t (v - v ) i= l d where l is the inductance value, t on is the on-time of the high-side mosfet, v out is the output voltage, and v in is the input voltage. therefore, the exact current-limit characteristic and maximum load capability are functions of the current-sense resistance, inductor value, and battery voltage. the positive valley current-limit threshold is preset for the MAX15569. see the electrical characteristics section. current limit using inductor dcr or sense resistors when using sense resistors or inductor dcr as current-sensing elements, calculate the required sense resistance (r sense ) with the following equation: lim(min) sense lx(valley) v r= i where i lx(valley) is the inductor valley current at ocp, and v ilim(min) is 38mv 3mv. carefully observe the pcb layout guidelines to ensure that noise and trace errors do not corrupt the current- sense signals seen by the current-sense inputs (csp_, csn_). current limit with the max15515 current sense when using the current-sensing method of the max15515, c alculate the csp_ - csn_ resistor (r csp_ ) using the following equation: lim(min) csp_ lx(valley) v r= ai where a is 10 -5 , i lx(valley) is the inductor valley current at ocp, and v ilim(min) is 38mv 3mv. current monitoring (imon) the device includes a current monitoring function. a simplified data-acquisition system is employed to convert the analog signals from the current-sense inputs to 8-bit values in the imon register (see figure 5 ). the adc con - verter filters the current-sense signal by averaging over eight samples. the acquisition rate is 100s. the content of the imon register is updated every 400s. the device includes a unidirectional transconductance amplifier that sources current proportional to the posi - tive current-sense voltage. the imon output current is defined by: i imon = g m(imon) x (v csp_ - v csn_ ) = g m(imon) x i load x r sense where g m(imon) is the transconductance-amplifier gain, as defined in the electrical characteristics section (5.12a/mv typ).an external resistor (r imon ) between imon and agnd sets the current monitor output voltage: v imon = i imon x r imon MAX15569 2-phase/1-phase quicktune-pwm controller with serial i 2 c interface www.maximintegrated.com maxim integrated 18 downloaded from: http:///
where r sense is the value of the effective current-sense resistance. choose r imon so that v imon is 2.56v at the full load current. c imon is the imon averaging capacitor. imon is sampled every 400s. choose c imon such that r imon x c imon gives a time constant of approximately 150s (see figure 5 ). the imon voltage is internally clamped to a maximum 3.2v (typ), preventing the imon output from exceeding the imon voltage rating even under overload or short- circuit conditions. imon is high impedance when in shutdown. feedback adjustment ampliier load-line ampliier (steady state and ac droop) the device includes a transconductance amplifier for controlling the load-line regardless of the sense imped - ance value. the input signal of the amplifier is the sum of the current-sense voltages (v csp1 , v csn1 , and v csp2 , v csn2 ), which differentially sense the current-sense volt - age. see figure 6 . the ac-droop amplifier output (fbac) connects to the remote-sense point of the output through a resistor network (r droop ) that sets the dc and ac current-loop gain: v out = v target - (r droop i fbac ) where the target voltage (v target ) is defined in the nominal output-voltage selection section, and fbac amplifiers output current (i fbac ) is determined by the current-sense voltage: i fbac = g m(fbac) (v csp_ - v csn_ ) where g m(fbac) = 1.2a/mv (typ), as defined in the electrical characteristics section. since the feedback voltage (v fb ) is regulated to the setvout voltage, the output voltage changes in response to the fbac current (i fbac ) to create a load-line with accuracy defined by the characteristics of the r droop network and g m(fbac) . the device supports flexible combinations of ac and dc load-lines: an ac load-line > dc load-line, an ac load-line = dc load-line, and an ac load-line < dc load-line. the effective impedance (z fbac ) between the output of the load-line transconductance amplifier (fbac) and the positive side of the remote-sensed output voltage sets the transient ac droop. the effective impedance (z fb ) between the feedback- sense input (fb) and the positive side of the feedback remote sense sets the static (dc) droop. figure 5. imon network csp1 r sense1 network csn1 g m(imon) i imon i imon (v csp1 - v csn1 ) csp2 r sense2 network csn2 r imon r imon = 2.56v/(r sense_ x g m(imon) x i out(max) ) c imon x r imon = 150s c imon v imon 3.2v imon clamp (v csp2 - v csn2 ) 8-bit dac 0 to 2.56v range imon register MAX15569 MAX15569 2-phase/1-phase quicktune-pwm controller with serial i 2 c interface www.maximintegrated.com maxim integrated 19 downloaded from: http:///
a capacitor from fbac to fb (c fbac ) couples the ac ripple from the output of the load-line transconduc - tance amplifier to the feedback sense input. ? an integrator on fb corrects for output ripple and ground-sense offset (see figure 6 ). when the device is used with differential current sensing: r ll r droop r sense g m(fbac) where r ll is the load-line, r sense is the effective current-sense resistance across csp_ and csn_. r droop is the effective resistance between the fbac output (for ac droop) or the fb input (for dc droop) and the positive side of the remote-sensed output voltage. see table 2 for ac- and dc-droop settings circuit con - figuration. when the inductors dcr is used as the current-sense element, the current-sense inputs should include an ntc thermistor to minimize the temperature dependence of the load-line variation due to the dcr temperature coef - ficient. fbac and fb are high impedance in shutdown. figure 6. fb network (load-line control and remote sensing) table 2. ac-droop and dc-droop settings dc load-line (mv/a) ac load-line (mv/a) r droop_ac r droop_dc r fb c fbac note 0 r ll_ac r fbac Ur fbs * 0 open c fbac r fbac = r fbs * r ll_dc r ll_ac r fbs * + r fb (r fbac = open) r fbs * (r fbac = open) r fb c fbac dc load-line < ac load-line r ll r ll open r fbs * 0? open dc load-line = ac load-line z fbac x i fbac sets the ac load-line z fb x i fbac sets the static load-line gnds fb fbac c fbac x r droop = t sw to (10 x t sw ) ripple- compensation capacitor r droop output r fbac 10 ? 10 ? 10 ? 10 ? r fb c fbac c fb 1nf c out c gnds 1nf r fbs high-frequency filter catch resistors so fb remains closed looped without cpu present cpu v cc sensecpu gnd sense MAX15569 ( csp_ - csn_) to error amplifier i fbac * see figure 6. MAX15569 2-phase/1-phase quicktune-pwm controller with serial i 2 c interface www.maximintegrated.com maxim integrated 20 downloaded from: http:///
differential output-voltage remote sense the device includes differential, remote-sense inputs to eliminate the effects of voltage drops along the pcb traces and through the power pins of the processor. the feedback-sense node connects to the load-line resistor/ capacitor network (r droop /c fbac ). the ground-sense (gnds) input connects to an amplifier that adjusts the feedback voltage to counteract the voltage drop in the ground plane. connect the load-line resistor (r droop ) and ground-sense (gnds) input directly to the remote- sense outputs of the processor, as shown in figure 6 . the correction range is bounded to less than 200mv. the remote-sense lines draw less than 0.5a to minimize the offset errors. steady-state integrator ampliier the device utilizes internal integrator amplifiers that force the dc average of the fb voltage to equal the target voltage, allowing accurate dc output-voltage regula - tion regardless of the output voltage. the integrator is designed to correct for the steady-state offsets/errors. nominal output-voltage selection the nominal no-load output voltage (v target ) is defined by the selected voltage reference, plus the remote ground-sense adjustment (v gnds ), as defined in the following equation: v target = v fb - v dac + v gnds where v dac is the selected output voltage. on startup, the device slews the target voltage from ground to the default 1v boot voltage unless a different voltage code is selected before en is pulled high. dynamic output-voltage transitions the devices transition time depends on the slew-rate setting, the selected setvout voltage difference, and the accuracy of the slew-rate controller (see the slew rate section in the electrical characteristics section). the slew rate is not dependent on the total output capacitance, as long as the required transition current plus existing load current remains below the current limit. for dynamic vid transitions, the transition time (t tran ) is given by: new old tran target v -v t= dv () dt where dv target /dt is the slew rate (register 0x06h), v old is the original output voltage, and v new is the new target voltage (see table 3 ). table 3. output-voltage selection line bit 7* bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 hex voltage 0 x 0 0 0 0 0 0 0 00h 0.000 1 x 0 0 0 0 0 0 1 01h 0.500 2 x 0 0 0 0 0 1 0 02h 0.510 3 x 0 0 0 0 0 1 1 03h 0.520 4 x 0 0 0 0 1 0 0 04h 0.530 5 x 0 0 0 0 1 0 1 05h 0.540 6 x 0 0 0 0 1 1 0 06h 0.550 7 x 0 0 0 0 1 1 1 07h 0.560 8 x 0 0 0 1 0 0 0 08h 0.570 9 x 0 0 0 1 0 0 1 09h 0.580 10 x 0 0 0 1 0 1 0 0ah 0.590 11 x 0 0 0 1 0 1 1 0bh 0.600 12 x 0 0 0 1 1 0 0 0ch 0.610 13 x 0 0 0 1 1 0 1 0dh 0.620 14 x 0 0 0 1 1 1 0 0eh 0.630 15 x 0 0 0 1 1 1 1 0fh 0.640 16 x 0 0 1 0 0 0 0 10h 0.650 17 x 0 0 1 0 0 0 1 11h 0.660 MAX15569 2-phase/1-phase quicktune-pwm controller with serial i 2 c interface www.maximintegrated.com maxim integrated 21 downloaded from: http:///
table 3. output-voltage selection (continued) line bit 7* bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 hex voltage 18 x 0 0 1 0 0 1 0 12h 0.670 19 x 0 0 1 0 0 1 1 13h 0.680 20 x 0 0 1 0 1 0 0 14h 0.690 21 x 0 0 1 0 1 0 1 15h 0.700 22 x 0 0 1 0 1 1 0 16h 0.710 23 x 0 0 1 0 1 1 1 17h 0.720 24 x 0 0 1 1 0 0 0 18h 0.730 25 x 0 0 1 1 0 0 1 19h 0.740 26 x 0 0 1 1 0 1 0 1ah 0.750 27 x 0 0 1 1 0 1 1 1bh 0.760 28 x 0 0 1 1 1 0 0 1ch 0.770 29 x 0 0 1 1 1 0 1 1dh 0.780 30 x 0 0 1 1 1 1 0 1eh 0.790 31 x 0 0 1 1 1 1 1 1fh 0.800 32 x 0 1 0 0 0 0 0 20h 0.810 33 x 0 1 0 0 0 0 1 21h 0.820 34 x 0 1 0 0 0 1 0 22h 0.830 35 x 0 1 0 0 0 1 1 23h 0.840 36 x 0 1 0 0 1 0 0 24h 0.850 37 x 0 1 0 0 1 0 1 25h 0.860 38 x 0 1 0 0 1 1 0 26h 0.870 39 x 0 1 0 0 1 1 1 27h 0.880 40 x 0 1 0 1 0 0 0 28h 0.890 41 x 0 1 0 1 0 0 1 29h 0.900 42 x 0 1 0 1 0 1 0 2ah 0.910 43 x 0 1 0 1 0 1 1 2bh 0.920 44 x 0 1 0 1 1 0 0 2ch 0.930 45 x 0 1 0 1 1 0 1 2dh 0.940 46 x 0 1 0 1 1 1 0 2eh 0.950 47 x 0 1 0 1 1 1 1 2fh 0.960 48 x 0 1 1 0 0 0 0 30h 0.970 49 x 0 1 1 0 0 0 1 31h 0.980 50 x 0 1 1 0 0 1 0 32h 0.990 51 x 0 1 1 0 0 1 1 33h 1.000 52 x 0 1 1 0 1 0 0 34h 1.010 53 x 0 1 1 0 1 0 1 35h 1.020 54 x 0 1 1 0 1 1 0 36h 1.030 55 x 0 1 1 0 1 1 1 37h 1.040 MAX15569 2-phase/1-phase quicktune-pwm controller with serial i 2 c interface www.maximintegrated.com maxim integrated 22 downloaded from: http:///
table 3. output-voltage selection (continued) line bit 7* bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 hex voltage 56 x 0 1 1 1 0 0 0 38h 1.050 57 x 0 1 1 1 0 0 1 39h 1.060 58 x 0 1 1 1 0 1 0 3ah 1.070 59 x 0 1 1 1 0 1 1 3bh 1.080 60 x 0 1 1 1 1 0 0 3ch 1.090 61 x 0 1 1 1 1 0 1 3dh 1.100 62 x 0 1 1 1 1 1 0 3eh 1.110 63 x 0 1 1 1 1 1 1 3fh 1.120 64 x 1 0 0 0 0 0 0 40h 1.130 65 x 1 0 0 0 0 0 1 41h 1.140 66 x 1 0 0 0 0 1 0 42h 1.150 67 x 1 0 0 0 0 1 1 43h 1.160 68 x 1 0 0 0 1 0 0 44h 1.170 69 x 1 0 0 0 1 0 1 45h 1.180 70 x 1 0 0 0 1 1 0 46h 1.190 71 x 1 0 0 0 1 1 1 47h 1.200 72 x 1 0 0 1 0 0 0 48h 1.210 73 x 1 0 0 1 0 0 1 49h 1.220 74 x 1 0 0 1 0 1 0 4ah 1.230 75 x 1 0 0 1 0 1 1 4bh 1.240 76 x 1 0 0 1 1 0 0 4ch 1.250 77 x 1 0 0 1 1 0 1 4dh 1.260 78 x 1 0 0 1 1 1 0 4eh 1.270 79 x 1 0 0 1 1 1 1 4fh 1.280 80 x 1 0 1 0 0 0 0 50h 1.290 81 x 1 0 1 0 0 0 1 51h 1.300 82 x 1 0 1 0 0 1 0 52h 1.310 83 x 1 0 1 0 0 1 1 53h 1.320 84 x 1 0 1 0 1 0 0 54h 1.330 85 x 1 0 1 0 1 0 1 55h 1.340 86 x 1 0 1 0 1 1 0 56h 1.350 87 x 1 0 1 0 1 1 1 57h 1.360 88 x 1 0 1 1 0 0 0 58h 1.370 89 x 1 0 1 1 0 0 1 59h 1.380 90 x 1 0 1 1 0 1 0 5ah 1.390 91 x 1 0 1 1 0 1 1 5bh 1.400 92 x 1 0 1 1 1 0 0 5ch 1.410 93 x 1 0 1 1 1 0 1 5dh 1.420 MAX15569 2-phase/1-phase quicktune-pwm controller with serial i 2 c interface www.maximintegrated.com maxim integrated 23 downloaded from: http:///
table 3. output-voltage selection (continued) * bit 7 is ignored (dont care), but listed here to match the voutmax register. x = dont care. note: dac codes above 1.6v are not advised due to proximity to the overvoltage threshold. line bit 7* bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 hex voltage 94 x 1 0 1 1 1 1 0 5eh 1.430 95 x 1 0 1 1 1 1 1 5fh 1.440 96 x 1 1 0 0 0 0 0 60h 1.450 97 x 1 1 0 0 0 0 1 61h 1.460 98 x 1 1 0 0 0 1 0 62h 1.470 99 x 1 1 0 0 0 1 1 63h 1.480 100 x 1 1 0 0 1 0 0 64h 1.490 101 x 1 1 0 0 1 0 1 65h 1.500 102 x 1 1 0 0 1 1 0 66h 1.510 103 x 1 1 0 0 1 1 1 67h 1.520 104 x 1 1 0 1 0 0 0 68h 1.530 105 x 1 1 0 1 0 0 1 69h 1.540 106 x 1 1 0 1 0 1 0 6ah 1.550 107 x 1 1 0 1 0 1 1 6bh 1.560 108 x 1 1 0 1 1 0 0 6ch 1.570 109 x 1 1 0 1 1 0 1 6dh 1.580 110 x 1 1 0 1 1 1 0 6eh 1.590 111 x 1 1 0 1 1 1 1 6fh 1.600 112 x 1 1 1 0 0 0 0 70h 1.610 113 x 1 1 1 0 0 0 1 71h 1.620 114 x 1 1 1 0 0 1 0 72h 1.630 115 x 1 1 1 0 0 1 1 73h 1.640 116 x 1 1 1 0 1 0 0 74h 1.650 117 x 1 1 1 0 1 0 1 75h 1.660 118 x 1 1 1 0 1 1 0 76h 1.670 119 x 1 1 1 0 1 1 1 77h 1.680 120 x 1 1 1 1 0 0 0 78h 1.690 121 x 1 1 1 1 0 0 1 79h 1.700 122 x 1 1 1 1 0 1 0 7ah 1.710 123 x 1 1 1 1 0 1 1 7bh 1.720 124 x 1 1 1 1 1 0 0 7ch 1.730 125 x 1 1 1 1 1 0 1 7dh 1.740 126 x 1 1 1 1 1 1 0 7eh 1.750 127 x 1 1 1 1 1 1 1 7fh 1.760 MAX15569 2-phase/1-phase quicktune-pwm controller with serial i 2 c interface www.maximintegrated.com maxim integrated 24 downloaded from: http:///
soft-start uses the slow slew rate, as set by the default setting in the srreg register, which is a fraction of the fast slew rate. see the slew-rate accuracy specification in the electrical characteristics section. the average induc - tor current per phase that is required to make an output-voltage transition is given by: out target l ph c dv i= n dt where dv target /dt is the required slew rate, c out is the total output capacitance, and n ph is the number of active phases. at the beginning of an output-voltage transition, the device blanks the int , so the open-drain output enters a high-impedance state during output-voltage transitions. the controller releases the int output approximately 4s (typ) after the slew-rate controller reaches the target output voltage. automatic pulse-skipping operation the device automatically operates with a 2-phase pulse- skipping control scheme. a logic-low level on drvskp enables the zero-crossing comparator of the driver (max17492) or power stage (max15515). therefore, these devices disable their low-side mosfets when they detect zero inductor current. this keeps the inductor from discharging the output capacitors and forces the controller to skip pulses under light-load conditions to avoid overcharging the output. if the system changes the vid code to a lower voltage, the device drives drvskp high to disable the pulse-skipping mode. this allows the regulator to actively discharge the output at the programmed slew rate. to disable pulse-skipping mode so the regulator continu - ally operates in forced-pwm operation, leave drvskp unconnected and connect the pulse-skipping control input on the driver or power stage to ground. automatic pulse-skipping switchover in pulse-skipping mode, an inherent automatic switchover to pfm takes place at light loads. this switchover is affect - ed by a comparator that truncates the low-side switch on-time at the inductor currents zero crossing. the zero- crossing detection is designed into the max17492 driver and the max15515 power stage. they sense the inductor current across the low-side mosfet. once the lx volt - age crosses the zero-crossing comparator threshold, the low-side mosfet turns off. this mechanism causes the threshold between pulse-skipping pfm and non-skipping pwm operation to coincide with the boundary between continuous and discontinuous inductor-current operation. the pfm/pwm crossover occurs when the load current of each phase is equal to 1/2 the peak-to-peak ripple current that is a function of the inductor value. even for wide 4.5v to 14v input voltage ranges, this crossover is relatively constant, with only a minor dependence on the input volt - age due to the typically low duty cycles. the total load cur - rent at the pfm/pwm crossover threshold (i load(skip )) is approximately: in out on load(skip) (v -v ) t i= 2l power-up sequence (por, uvlo) power-on reset (por) occurs when v bias and v tt rise above approximately 2v. por resets the fault latch and loads the default register settings. the v bias uvlo circuitry inhibits switching until v bias rises above 4.5v. the controller powers up the reference once the system enables the controller, v bias is above 4.5v, and en is driven high (see figure 2 ). with the reference in regulation, the controller ramps up to the selected output voltage (register 0x07h) at the selected slow slew rate (register 0x06h) after this initialization, the pwm controller begins switching: boot tran(start) target v t= (dv /dt) where dv target /dt is the slew rate. the soft-start slew rate is the slow slew rate set by the default setting in the srreg register. the soft-start circuitry does not use a variable current limit, so full output current is available immediately. interrupt ( int ) the device provides an active-low interrupt output ( int ) to indicate that the startup sequence is complete and the output voltage has moved to the programmed vid value. this signal is intended for system monitoring of the device . int remains high impedance during normal dc-dc operation. the controller asserts int to alert the system of an alarm event or if a fault condition occurs. see the alarms and fault protection (latched) sections for details (and figure 7 ). use an external pullup resistor between int and 3.3v to deliver a valid logic-level output. MAX15569 2-phase/1-phase quicktune-pwm controller with serial i 2 c interface www.maximintegrated.com maxim integrated 25 downloaded from: http:///
alarms temperature comparator (vrhot) the device features an independent comparator with input at therm. this comparator has an accurate thresh - old of 0.5 x v bias . use a 100k? ntc with a of 4250k. the ntc resistance drops to 5.68k? when the tempera - ture reaches +100c. the ntc forms a divider with the internal 5.35k? pullup resistance, so the voltage drops below the 0.5 x v bias threshold. vrhot is then asserted. the internal 5.35k? resistor is disconnected in shutdown, saving power. overcurrent warning (oc) the device includes an overcurrent-warning threshold that samples the phase 1 current-sense signal before each phase 1 on-time. when the csp1 - csn1 voltage exceeds the 23mv (typ) threshold, the status bit (d2) in register 0x04h) is asserted. if the warning is not masked, the controller asserts the int output to alert the system to the overcurrent condition. the fixed 23mv oc_alarm threshold is 15mv lower than the valley current-limit threshold to provide sufficient design margin before the regulator limits the output current. additionally, the controller includes a imon register that can be monitored by the system. output-code violation (voutmax) the controller includes a maximum output register (voutmax register 0x02h) to protect against target output voltage codes that could violate the absolute maxi - mum rating of the load. the value of this configuration register limits the output range. if a target output voltage is loaded into register 0x07h, the regulator sets the appro - priate status bit. if the warning is not masked, the control - ler asserts the int output to alert the system to the over - current condition. the output voltage attempts to ramp to the new target, but the regulator effectively clamps the output to the voutmax voltage to avoid an overvoltage condition. see the i 2 c commands and registers section for additional details. figure 7. startup sequence t en = 0ns t cal t ss t ss t strt v bias v tt v out enable int MAX15569 2-phase/1-phase quicktune-pwm controller with serial i 2 c interface www.maximintegrated.com maxim integrated 26 downloaded from: http:///
fault protection (latched) ton open-circuit protection the ton input includes open-circuit protection to avoid long, uncontrolled on-times that could result in an over - voltage condition on the output. the device detects an open-circuit fault if the ton current drops below 6a (typ) for any reason (e.g., the ton resistor (r ton ) is unpopulated, a high-resistance value is used, the input voltage is low, etc.). under these conditions, the device stops switching (drvpwm_ outputs become high imped - ance and drvskp is pulled low) and immediately sets the fault latch. toggle en or cycle power (bias) below 1v to clear the fault latch and reactivate the controller. the ton open- circuit fault is not indicated in the status register. output overvoltage protection (ovp) the ovp circuit is designed to protect the load against a shorted high-side mosfet by drawing high current and activating the adapter or battery protection circuits. the device continuously monitors the output for an overvolt - age fault. an ovp fault is detected if the output voltage exceeds the vid dac voltage by more than 300mv (min), or the fixed 1.83v (typ) threshold during a downward vid transition in skip mode. during pulse-skipping operation, the ovp threshold tracks the vid dac voltage as soon as the output is in regulation; otherwise, the fixed 1.83v (typ) threshold is used. when the ovp circuit detects an overvoltage fault, the drvpwm_ outputs become high impedance and the drvskp output is pulled high. ovp is disabled in the standby power state (en pulled low). after the fault condition occurs, the i 2 c interface remains active so the status register can be read to determine what triggered the fault. toggle en or cycle power (bias) below 1v to clear the fault latch. with the fault latch cleared and the fault condition removed, the regulator powers back up and the fault conditions are deasserted in the status register. output undervoltage protection (uvp) if the output voltage is 200mv (min) below the target volt - age and stays below this level for 200s (typ), the con - troller activates the shutdown sequence. the regulator turns on a 2k? discharge resistor and sets the fault latch. drvpwm_ outputs go to the high-impedance mode and drvskp is pulled low. after the fault condition occurs, the i 2 c interface remains active so the status register can be read to determine what triggered the fault. toggle en or cycle power (bias) below 1v to clear the fault latch. with the fault latch cleared and the fault condition removed, the regulator powers back up and the fault conditions are deasserted in the status register. thermal-fault protection (tshdn) the device features an internal thermal-fault protec - tion circuit. when the junction temperature rises above +160c, a thermal sensor sets the fault latch and drvpwm_ becomes high impedance. after the fault condition occurs, the i 2 c interface remains active so the status register can be read to determine what triggered the fault. toggle en or cycle power (bias) below 1v to clear the fault latch. with the fault latch cleared, the regulator powers back up and the fault condi - tions are deasserted in the status register, as long as the regulator has cooled by 15c (typ). external driver and disabling phases the device supports an external driver (max15515) for both phases. the drvpwm_ outputs provide the signals to trigger the drivers. connecting csp2 to bias of the device disables the second phase. the device provides a pulse-skipping-mode control output ( drvskp ) for the external driver control. drvskp goes high when the controller detects an output overvoltage- fault condition. drvskp is high during output-voltage transitions. the drvskp output is unconnected in shut - down. i 2 c interface, commands, registers, and digital control a simplified register summery of the i 2 c interface for the device is shown in table 4 . the i 2 c interface consists of a high-speed transceiver capable of 3.4mhz data rate. regulator address the device does not feature programmable addressing. these devices are hard-coded with bus address 70h . MAX15569 2-phase/1-phase quicktune-pwm controller with serial i 2 c interface www.maximintegrated.com maxim integrated 27 downloaded from: http:///
i 2 c commands and registers the device supports the following commands and registers shown in table 4 . voutmax control (0x02h) this register is programmed by the bus master to the maximum output voltage the regulator is allowed to sup - port. any attempts to set the setvout above voutmax are acknowledged by setting the output voltage to the content of the voutmax register. the default value is 51h (1.3v). see table 5 for bit descriptions. regulator status (0x04h)this register consists of six flags that determine the status of the regulator in case of thermal warning, overvoltage fault, undervoltage fault, output overcurrent warning, and maximum output violation. the int bit (d0) is asserted in case of any unmasked event. see table 6 for bit descrip - tions. 1) the vrhot bit (d5) is set when the voltage at therm pin goes below its nominal threshold (see the electrical characteristics section). 2) the uv bit (d4) is set when the output voltage drops 200mv lower than setvout value for 200s. table 4. i 2 c command and data register summary command master payload slave payload description hex name write read 00h reserved. 01h reserved. 02h voutmax conigures maximum output code returns maximum output code the maximum allowable output voltage (0.510v to 1.76v) that can be set by user. in case the i 2 c interface receives a set voltage command higher than the voutmax value, the regulator slews the output to voutmax set voltage. default is 51h (1.3v). 03h reserved. 04h status regulator status bits d[5:0] of this register consist of the vrhot lag (bit d5), undervoltage lag (bit d4), overvoltage lag (bit d3), overcurrent lag (bit d2), voutmax lag (bit d1), and int lag (bit d0). bits d[7:6] are not used and return 0. for a detailed description, see the regulator status (0x04h) section. the status register is set regardless of the mask register (0x05) content. 05h mask conigures mask status current mask status writing to this register prevents the assertion of the int output when the speciic fault or alarm is masked. this register does not mask the status register indication. default is 00h (no masking). 06h slew_rate conigures the output-voltage slew rate returns the output-voltage slew rate writing to this register sets the slew rate (volt/second) of the output voltage during the initial startup and dynamic output-voltage transitions. default is 04h (4.5mv/s for soft-start and 9mv/s for dynamic transitions). 07h setvout selects the output code returns the output code the 07h command sets the target output voltage. the regulator transitions up or down to the new output voltage 0.5s after the command is acknowledged. default is 33h (1v). 08h imon returns the output current value this register returns the average output current value. imon is updated every 400s. MAX15569 2-phase/1-phase quicktune-pwm controller with serial i 2 c interface www.maximintegrated.com maxim integrated 28 downloaded from: http:///
3) the ov bit (d3) is set when the output voltage rises 300mv above (or 1.83v fixed) the output voltage. 4) the oc bit (d2) is set when the valley of (csp1 - csn1) current signal exceeds 23mv (oc_alarm). the current-limit protection threshold is 15mv higher than the oc_alarm. 5) the vmerr bit (d1) is set in case the setvout exceeds the content of voutmax. changing setvout to values lower than voutmax clears the vmerr warn - ing. 6) masking of the status bit only prevents the int bit (d0) from being set by the specific status bit. the status bit is still set if the fault occurs, regardless of the status mask setting. the oc bit (d2) is sticky, but it does not hold int low when the oc fault goes away. this allows the system to determine what event triggered int to go low. all other fault bits are not sticky. reading the register after the oc event clears the flag. mask status (0x05h)masking of the status bit only prevents the int bit (d0) from being set by the specific status bit. the status bit is still set if the fault occurs, regardless of the status mask setting. see table 7 for bit descriptions. table 5. voutmax (maximum output voltage allowed) table 6. status (regulator status) x = dont care. i 2 c command default type d7 d6 d5 d4 d3 d2 d1 d0 0x02h 0x51h vmax_7 vmax_6 vmax_5 vmax_4 vmax_3 vmax_2 vmax_1 vmax_0 bit name description d7 vmax_7 r/w dont care bit. returns 0 when read. d6 vmax_6 r/w msb of the maximum allowed output voltage code. d5 vmax_5 r/w d4 vmax_4 r/w d3 vmax_3 r/w d2 vmax_2 r/w d1 vmax_1 r/w d0 vmax_0 r/w lsb of the maximum allowed output voltage code. 10mv resolution. i 2 c command default type d7 d6 d5 d4 d3 d2 d1 d0 0x04h 0x00h x x vrhot uv ov oc vmerr int# bit name description d7 r always reads 0. d6 r always reads 0. d5 vrhot r vrhot d4 uv r uv (v out undervoltage) d3 ov r ov (v out overvoltage) d2 oc r oc (output current over current limit). this bit is sticky and cleared when read if the oc fault is no longer present. d1 vmerr r voutmax error. set = 1 if (vid > voutmax ) d0 int r nored bits d[5:1], read-only, sets the int output. MAX15569 2-phase/1-phase quicktune-pwm controller with serial i 2 c interface www.maximintegrated.com maxim integrated 29 downloaded from: http:///
table 7. mask (regulator status mask register) x = dont care. note: in the event of uv, oc, ov, vrhot, or vmerr, the signal is anded by the complement of the mask regi ster content. x = dont care. figure 8. status bit masking table 8. srreg (slew-rate setting register) i 2 c command default type d7 d6 d5 d4 d3 d2 d1 d0 0x05h 0x00h x x vrhmsk uvmsk ovmsk ocmsk vmerrmsk reserved bit name description d7 r always reads 0. d6 r always reads 0. d5 vrhmsk r/w vrhot masking bit. d4 uvmsk r/w undervoltage-fault masking bit. d3 ovmsk r/w overvoltage-fault masking bit. d2 ocmsk r/w overcurrent-fault masking bit. d1 vmerrmsk r/w voutmax error masking bit. d0 r always reads 0. i 2 c command default type d7 d6 d5 d4 d3 d2 d1 d0 0x06h 0x04h x x srreg_5 srreg_4 srreg_3 srreg_2 srreg_1 srreg_0 bit name description d7 r/w see table 9 d6 r/w see table 9 d5 srreg_5 r/w see table 9 d4 srreg_4 r/w see table 9 d3 srreg_3 r/w see table 9 d2 srreg_2 r/w see table 9 d1 srreg_1 r/w see table 9 d0 srreg_0 r/w see table 9 status register mask register status bit 0(int state) intoutput pin other status logic fault or alarm event MAX15569 2-phase/1-phase quicktune-pwm controller with serial i 2 c interface www.maximintegrated.com maxim integrated 30 downloaded from: http:///
slew-rate coniguration (0x06h)the content of the srreg register determines the slew rate at both initial startup and dynamic output-voltage transition. there are 52 possibilities of selectable slew rates (4.5mv/s to 44mv/s) that cover the initial startup (soft-start) and dynamic output-voltage transition with different slew rates in one setting. see table 8 for bit descriptions and table 9 for slew-rate selections. table 9. slew-rate selections (register 0x06h) d7 d6 d5 d4 d3 d2 d1 d0 soft-start slew rate (mv/s) regular slew rate (mv/s) x x 0 0 0 0 0 0 18 18 x x 0 0 0 0 0 1 9 18 x x 0 0 0 0 1 0 4.5 18 x x 0 0 0 0 1 1 9 9 x x 0 0 0 1 0 0 4.5* 9* x x 0 0 0 1 0 1 36 36 x x 0 0 0 1 1 0 18 36 x x 0 0 0 1 1 1 9 36 x x 0 0 1 0 0 0 4.5 36 x x 0 0 1 0 0 1 4.5 4.5 x x 0 0 1 0 1 x 4.5 9 x x 0 0 1 1 0 x 4.5 9 x x 0 0 1 1 1 0 4.5 9 x x 0 1 0 0 0 0 22 22 x x 0 1 0 0 0 1 11 22 x x 0 1 0 0 1 0 5.5 22 x x 0 1 0 0 1 1 11 11 x x 0 1 0 1 0 0 5.5 11 x x 0 1 0 1 0 1 44 44 x x 0 1 0 1 1 0 22 44 x x 0 1 0 1 1 1 11 44 x x 0 1 1 0 0 0 5.5 44 x x 0 1 1 0 0 1 5.5 5.5 x x 0 1 1 0 x x 5.5 11 x x 0 1 1 1 1 0 5.5 11 x x 1 0 0 0 0 0 14 14 x x 1 0 0 0 0 1 7 14 x x 1 0 0 0 1 0 3.5 14 x x 1 0 0 0 1 1 7 7 x x 1 0 0 1 0 0 3.5 7 x x 1 0 0 1 0 1 28 28 MAX15569 2-phase/1-phase quicktune-pwm controller with serial i 2 c interface www.maximintegrated.com maxim integrated 31 downloaded from: http:///
table 9. slew-rate selections (register 0x06h) (continued) * por default setting. x = dont care. d7 d6 d5 d4 d3 d2 d1 d0 soft-start slew rate (mv/s) regular slew rate (mv/s) x x 1 0 0 1 1 0 14 28 x x 1 0 0 1 1 1 7 28 x x 1 0 1 0 0 0 3.5 28 x x 1 0 1 0 0 1 3.5 3.5 x x 1 0 1 0 1 0 3.5 7 x x 1 0 1 0 1 1 3.5 7 x x 1 0 1 1 0 0 3.5 7 x x 1 0 1 1 0 1 3.5 7 x x 1 0 1 1 1 0 3.5 7 x x 1 1 0 0 0 0 18 18 x x 1 1 0 0 0 1 9 18 x x 1 1 0 0 1 0 4.5 18 x x 1 1 0 0 1 1 9 9 x x 1 1 0 1 0 0 4.5 9 x x 1 1 0 1 0 1 36 36 x x 1 1 0 1 1 0 18 36 x x 1 1 0 1 1 1 9 36 x x 1 1 1 0 0 0 4.5 36 x x 1 1 1 0 0 1 4.5 4.5 x x 1 1 1 0 x x 4.5 9 x x 1 1 1 1 1 0 4.5 9 MAX15569 2-phase/1-phase quicktune-pwm controller with serial i 2 c interface www.maximintegrated.com maxim integrated 32 downloaded from: http:///
output-voltage set register (0x07h) the setvout register slews the output voltage 0.5s after the setvout command is acknowledged. the slew rate of the change in output voltage is equal to the value set by srreg. the device dac supports volt - ages between 0.5v and 1.6v. see table 3 for the output- voltage codes and table 10 for bit descriptions. current monitor register (0x08h) the device includes a current monitoring function. an internal adc converts the analog signals from the imon pin output to 8-bit values in the imon register. the adc converter filters the current-sense signal by averaging over four samples. the acquisition rate is 100s. the content of this register is updated every 400s. for more information on how to set the desired value for imon resolution, see the current monitoring (imon) section. see table 11 for bit descriptions. table 10. setvout (output-voltage set register) table 11. imon (current monitor register) i 2 c command default type d7 d6 d5 d4 d3 d2 d1 d0 0x07 0x33 vid_7 vid_6 vid_5 vid_4 vid_3 vid_2 vid_1 vid_0 bit name description d7 vid_7 r dont care bit. returns 0 when read. d6 vid_6 r msb of the maximum allowed output voltage code d5 vid_5 r see table 3 for the actual output-voltage code. d4 vid_4 r d3 vid_3 r d2 vid_2 r d1 vid_1 r d0 vid_0 r lsb of the maximum allowed output-voltage code. 10mv resolution. i 2 c command default type d7 d6 d5 d4 d3 d2 d1 d0 0x08h 0x00h bit name description d7 im_7 r d6 im_6 r d5 im_5 r d4 im_4 r d3 im_3 r d2 im_2 r d1 im_1 r d0 im_0 r MAX15569 2-phase/1-phase quicktune-pwm controller with serial i 2 c interface www.maximintegrated.com maxim integrated 33 downloaded from: http:///
multiphase quicktune-pwm design procedure firmly establish the input voltage range and maximum load current before choosing a switching frequency and inductor operating point (ripple-current ratio). the primary design trade-off lies in choosing a good switching frequency and inductor operating point, and the following four factors dictate the rest of the design: 1) input voltage range: the maximum value (v in(max) ) must accommodate the worst-case high ac adapt - er voltage. the minimum value (v in(min) ) must account for the lowest input voltage after drops due to connectors, fuses, and battery selector switches. if there is a choice at all, lower input voltages result in better efficiency. 2) maximum load current: there are two values to consider. the peak load current (i load(max) ) deter - mines the instantaneous component stresses and filtering requirements, and drives output-capacitor selection, inductor saturation rating, and the design of the current-limit circuit. the continuous-load current (i load ) determines the thermal stresses and drives the selection of the input capacitors, mosfets, and other critical heat-contributing components. modern notebook cpus generally exhibit i load = 0.8 x i load(max) . for multiphase systems, each phase supports a fraction of the load, depending on the current balancing. when properly balanced, the load current is evenly distributed among phases: load load(phase) ph i i n = where n ph is the total number of active phases. 3) switching frequency: this choice determines the basic trade-off between size and efficiency. the optimal frequency is largely a function of maximum input voltage due to mosfet switching losses that are proportional to frequency and v in 2 . the optimum frequency is also a moving target due to rapid improvements in mosfet technology that are making higher frequencies more practical. 4) inductor operation point: this choice provides trade- offs between size vs. efficiency and transient respons - es vs. output noise. low inductor values provide better transient response and smaller physical size, but also result in lower efficiency and higher output noise due to increased ripple current. the minimum practical inductor value is one that causes the circuit to operate at the edge of critical conduction (where the inductor current just touches zero with every cycle at maximum load). inductor values lower than this grant no further size-reduction benefit. the optimum operating point is usually between 30% and 50% ripple current. for a multiphase core regulator, select an lir value of ~0.4. inductor selection the switching frequency and operating point (% ripple current or lir) determine the inductor value as follows: v -v v in out out ln ph f i lir v sw load(max) in = ?? ?? ?? ?? ?? ?? ?? where n ph is the total number of phases. find a low-loss inductor having the lowest possible dc resistance that fits in the allotted dimensions. the core must not saturate at the peak-inductor current (i peak ): i lir load(max) i1 peak n2 ph = + ?? ?? ?? ?? ?? ?? ?? output capacitor selection output capacitor selection is determined by the controller stability and the transient soar and sag requirements of the application. output capacitor esr the output filter capacitor must have low enough effective series resistance (esr) to meet output-ripple and load-transient requirements, yet have high enough esr to satisfy stability requirements. in cpu v core converters and other applications where the output is subject to large-load transients, the size of the output capacitor typically depends on how much esr is needed to prevent the output from dipping too low under a load transient. ignoring the sag due to finite capacitance: step esr pcb load(max) v (r r ) i + d the output-voltage ripple of a step-down controller equals the total inductor ripple current multiplied by the output capacitors esr. when operating multiphase out-of- phase systems, the peak inductor currents of each phase are staggered, resulting in lower output ripple voltage by reducing the total inductor ripple current. for multiphase operation, the maximum esr to meet ripple requirements is given in the following equation: in sw esr ripple in ph out out vf l rv (v (n v ))v ?? ?? ? ?? where nph is the total number of active phases and f sw is the switching frequency per phase. MAX15569 2-phase/1-phase quicktune-pwm controller with serial i 2 c interface www.maximintegrated.com maxim integrated 34 downloaded from: http:///
the actual capacitance value required relates to the physical size needed to achieve low esr, as well as to the chemistry of the capacitor technology. the capacitor is usually selected by esr and voltage rating rather than by capacitance value (this is true for polymer types). when using low-capacity ceramic filter capacitors, capacitor size is usually determined by the capacity needed to prevent v sag and v soar from causing problems during load transients. generally, once enough capacitance is added to meet the overshoot requirement, undershoot at the rising load edge is no longer a problem (see the v sag and v soar equations in the transient response section). output capacitor stability considerations for quicktune-pwm controllers, stability is determined by the value of the esr zero relative to the switching frequency. the boundary of instability is given by the following equation: sw esr f f where: esr eff out 1 f 2r c = and: eff esr ll pcb r r rr = ++ where c out is the total output capacitance, r esr is the total equivalent series resistance, r ll is the load-line gain, and r pcb is the parasitic board resistance between the output capacitors and sense resistors. for a 1mhz application, the esr zero frequency must be well below 300khz, preferably below 100khz. sanyo poscap and panasonic sp capacitors are widely used and have typical esr zero frequencies below 100khz. ceramic capacitors have a high-esr zero frequency, but applications with significant load-line (dc-coupled or ac-coupled) can take advantage of their size and low esr. when using only ceramic output capacitors, output overshoot (v soar ) typically determines the mini - mum output-capacitance requirement. their relatively low capacitance value favors high-switching-frequency operation with small inductor values to minimize the energy transferred from inductor to capacitor during load- step recovery. unstable operation manifests itself in two related but distinctly different ways: double pulsing and feedback-loop instability. double pulsing and feedback-loop instability double pulsing occurs due to noise on the output or because the esr is so low that there is not enough volt - age ramp in the output-voltage signal. this fools the error comparator into triggering a new cycle immediately after the minimum off-time period has expired. double pulsing is more annoying than harmful, resulting in nothing worse than increased output ripple. however, it can indicate the possible presence of loop instability due to insufficient esr. loop instability can result in oscillations at the out - put after line or load steps. such perturbations are usually damped, but can cause the output voltage to rise above or fall below the tolerance limits. the easiest method for checking stability is to apply a very fast 10% to 90% maximum load transient and carefully observe the output- voltage ripple envelope for overshoot and ringing. it can help to simultaneously monitor the inductor current with an ac current probe. do not allow more than one cycle of ringing after the initial step-response under/overshoot. transient response the inductor-ripple current impacts transient-response performance, especially at low v in - v out differentials. low inductor values allow the inductor current to slew faster, replenishing charge removed from the output filter capacitors by a sudden load step. the amount of output sag is also a function of the maximum duty factor, which can be calculated from the on-time and minimum off-time. for a multiphase controller, the worst-case output sag voltage can be determined by: 2 load(max) min sag ph out out sw min l( i ) t v 2n c v t - t d ? ???? and: min on off(min) t tt = + where t off(min) is the minimum off-time (see the electrical characteristics section), t sw is the programmed switch - ing period, and n ph is the total number of active phases. v sag must be less than the transient droop, i load(max) x r ll . the capacitive soar voltage due to stored inductor energy can be calculated as: 2 load(max) soar ph out out (i )l v 2n c v d the actual peak of the soar voltage depends on the time where the decaying esr step and rising capacitive soar are at their maximum. this is best simulated or measured. MAX15569 2-phase/1-phase quicktune-pwm controller with serial i 2 c interface www.maximintegrated.com maxim integrated 35 downloaded from: http:///
input capacitor selection the input capacitor must meet the ripple-current require - ment (i rms ) imposed by the switching currents. the multiphase quicktune-pwm controllers operate out-of phase, reducing the rms input. the i rms requirements can be determined by the following equation: ( ) ( ) load rms ph out in ph out ph in i i nv v- nv nv ?? = ?? ?? the worst-case rms current requirement occurs when operating with v in = 2 (n ph v out ). therefore, the above equation simplifies to i rms = 0.5 x (i load/nph ). choose an input capacitor that exhibits less than 10c temperature rise at the rms input current for optimal circuit longevity. applications information pcb layout guidelines careful pcb layout is critical to achieve low switching losses and clean, stable operation. the switching power stage requires particular attention. if possible, mount all the power components on the top side of the board, with their ground terminals flush against one another. the layout of the device is intimately related to the layout of the cpu. the high-current output paths from the regulator must flow cleanly into the high-current inputs on the processor. for vr12.6 processors, these inputs are orthogonal. this arrangement effectively forces the regulator to be located diagonally, with respect to the processor. refer to the MAX15569 evaluation kit speci - fications for layout examples and follow these guidelines for good pcb layout: keep the high-current paths short, especially at the ground terminals. this is essential for stable, jitter-free operation. connect all analog grounds to a separate solid- copper plane that connects to the ground pin of the quicktune-pwm controller. this includes the v bias bypass capacitor, fb, and gnds bypass capacitors. keep the power traces and load connections short. this is essential for high efficiency. the use of thick copper pcb (2oz vs. 1oz) can enhance full-load efficiency by 1% or more. correctly routing pcb traces is a difficult task that must be approached in terms of fractions of centimeters, where a single m? of excess trace resistance causes a measurable efficiency penalty. csp_ and csn_ connections for current limiting, load- line control, and current monitoring must be made using kelvin-sense connections to guarantee the current-sense accuracy. when trade-offs in trace lengths must be made, it is preferable to allow the inductor charging path to be made longer than the discharge path. for example, it is better to allow some extra distance between the input capacitors and the high-side mosfet than to allow distance between the inductor and the low-side mosfet, or between the inductor and the output filter capacitor. route high-speed switching nodes away from sensi - tive analog areas (i.e., fb, fbac, csp_, csn_, etc.). see table 12 for layout procedures. MAX15569 2-phase/1-phase quicktune-pwm controller with serial i 2 c interface www.maximintegrated.com maxim integrated 36 downloaded from: http:///
table 12. layout procedures components description capacitors the general rule is that capacitors take priority over resistors since they provide a iltering funct ion. the list below is in order of priority: 1) v bias capacitors: place these near the ic pins with wide traces and good connection to pgnd. 2) csp_ - csn_ differential filter capacitors: place the capacitors and the step resistor near the ic pins. these inputs are critical because they are used for regulation and load-line, as well as current limit and current balance. 3) common-mode capacitors: the capacitors to agnd take the next priority. 4) fb and gnds capacitors: the fb capacitor can be slightly farther away from the ic since the fb resistor has priority to be closer to the ic. fb and fbac the fb and fbac resistors should be near the respective pins. keep the trace short to reduce any inductance. current sense use kelvin-sense connection to the sense element (inductor or sense resistor). route csp_ traces near csn_. avoid any switching signals, especially lx when routing these current-sensing signals. thermistors the ntc for therm sensing should be placed near the power components of the irst phase. catch resistors catch resistors should be placed near the point of load so that the output-voltage trace does not need to route back to the ic. the ground catch resistor is less critical as it only requires a via to connect to t he pgnd plane. remote sense route together in a quiet layer, avoiding any switching signals, especially lx. i 2 c pullups for i 2 c interface and int do not need to be too close to the ic and can be placed farther away to make space for other more important components near the ic. place a small 0.1f decoupling capacitor for the v tt near the pullup resistors. agnd keep the agnd polygon just large enough to cover agnd components. do not make it any larger than necessary. the agnd polygon should not run under any high-voltage switching traces since all agnd connections should be on the other side of the ic, away from the driver pins. agnd-pgnd agnd-pgnd connection should be made away from the pgnd pins so as not to be in the path of the drvpwm_ drive currents. a good location is near the bias pin. exposed pad connect to agnd. power components place the power components close to keep the current loop small. avoid large lx nodes. use multiple vias to keep the impedance low and to carry the high currents. MAX15569 2-phase/1-phase quicktune-pwm controller with serial i 2 c interface www.maximintegrated.com maxim integrated 37 downloaded from: http:///
+denotes a lead(pb)-free/rohs-compliant package. *ep = exposed pad. part temp range pin-package MAX15569gtg+ -40c to +105c 24 tqfn-ep* package type package code outline no. land pattern no. 24 tqfn-ep t2444+4 21-0139 90-0022 MAX15569 2-phase/1-phase quicktune-pwm controller with serial i 2 c interface www.maximintegrated.com maxim integrated 38 package information for the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. chip information process: bicmos ordering information downloaded from: http:///
revision number revision date description pages changed 0 3/13 initial release 1 2/15 updated the beneits and features section 1 maxim integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim integrated product. no circuit patent licenses are implied. maxim integrated reserves the right to change the circuitry and speciications without n otice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. maxim integrated and the maxim integrated logo are trademarks of maxim integrated products, inc. ? 2015 maxim integrated products, inc. 39 MAX15569 2-phase/1-phase quicktune-pwm controller with serial i 2 c interface revision history for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim integrateds website at www.maximintegrated.com. downloaded from: http:///

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